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An Accurate Methodology for Transmitter Silicon Jitter Measurement in a Server Product Validation Setup

Mohiuddin Mazumder  (Principal Engineer, Intel Corporation)

Location: Ballroom C

Date: Thursday, January 30

Time: 2:50pm - 3:30pm

Track: 08. Measurement, Simulation & Improving Jitter, Noise & BER (Pre & Post FEC), 12. Applying Test & Measurement Methodology

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

An automated Electrical Validation (EV) setup for a 4000+ square millimeter server package with hundreds of I/O lanes can introduce 15+ dB channel at Nyquist frequency between the transmitter (Tx) diepad and the oscilloscope input where the transmitted signal is captured for analysis. The traditional de-embedding based jitter extraction methodology introduces greater than 200% error in some of the measured Tx jitter parameters at 16 and 32 Gbps. In this paper, we present an accurate methodology of measuring the Tx jitter parameters by an optimal combination of Tx equalization and a CTLE-based software equalization. We also provide guidelines for EV board design, measurement setup, and equipment quality to further minimize error in Tx jitter measurement.


The S-parameter based de-embedding methodology of Tx jitter extraction is error-prone when the loss between Tx diepad and oscilloscope input exceeds 10 dB at Nyquist frequency. An accurate methodology with an optimal combination of Tx and a CTLE-based equalization can mitigate the issue leading to cost-effective validation of high-speed links.

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