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An Efficient Power & Signal Integrity Combo Simulation & Correlation for DDR4 & Beyond

Thomas To (Technical Director, Xilinix)

Juan Wang (Senior Staff Engineer, Xilinx)

Xi (Sean) Long (Senior Engineer, Xilinx)

Location: Ballroom F

Date: Thursday, January 31

Time: 2:50pm - 3:30pm

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Understanding the power supply integrity together with signal integrity is ever more important as the system scales to DDR4 top speed and beyond. This paper proposes an efficient combo simulation by injecting realistic power supply noise tones according to the system usage model. The power network is based on a real design and the stimulus is based on real usage model from the memory controller unit. The paper will show the method to optimally capture the necessary feature behavior for the modeling. The analysis will be correlated to an actual lab measurement in this paper.


An efficient method to combine power supply noise, which is based on actual usage model, with signal integrity analysis is presented. This approach enables remove the conservatism in estimating system channel jitter for DDR4 system and beyond.

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