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Analysis of Power Integrity Effects on Signal Integrity in FPGA DDR4 Memory Interfaces by Using PDN Resonance Peaks Based Worst Case Data Patterns

Cosmin Iorga (Principal R&D,

Cristian Filip (Product Architect High-Speed Analysis Products, Mentor, A Siemens Business)

Daniel de Araujo (Principal Product Architect, Mentor, a Siemens Business)

Nitin Bhagwath (Product Architect, Mentor, a Siemens Business)

Hans Klos (Managing Director Sintecs BV, Sintecs)

Arpad Muranyi (Senior Product Architect, Mentor, A Siemens Business)

Chuck Ferry (Systems Architect Director, Mentor, A Siemens Business)

Praveen Anmula (Product Architect, Mentor, A Siemens Business)

Location: Ballroom E

Date: Wednesday, January 30

Time: 2:00pm - 2:40pm

Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 06. Applying Chip-to-Chip and Advanced PCB Design & Simulation Techniques

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Power integrity effects on signal integrity in FPGA DDR4 memory interfaces are analyzed in pre-layout, post-layout, and system validation data patterns created based on the resonance peaks of the power distribution network (PDN). The PDN impedance profile is measured with an FPGA configured vector network analyzer (VNA). Multiple test data patterns are created to superimpose the power supply current frequency spectral components with the PDN resonance peaks and to exercise transmission line multiple reflections build-up effect. These data patterns are then used to identify the dominant contributors to signal integrity degradation.


Attendants will learn a technique for identifying the dominant contributors of signal integrity degradation in high-speed interfaces, such as DDR4, using a statistical analysis approach for model extraction and worst case specific data patterns that exercise PDN resonant peaks and transmission line multiple reflections for simulation and validation.

Intended Audience


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