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Analysis on Power Via Induced Quasi-Quarter-Wavelength Resonance for Crosstalk Reduction

DongHyun (Bill) Kim (Assistant Professor, Missouri University of Science and Technology)

Siqi Bai (PhD Student, Missouri University of Science and Technology)

Junda Wang (MS Student, Missouri University of Science and Technology)

Junyong Park (Ph.D. Student, Korea Advanced Institute of Science and Technology)

Jongjoo Lee (Research Scholar, Missouri University of Science and Technology)

Bichen Chen (Network Hardware Engineer, Facebook, Inc.)

Srinivas Venkataraman (Signal Integrity Engineer, Facebook, Inc.)

Xu Wang (Hardware Engineer, Facebook, Inc.)

Siqi Bai (Cynthia Tang Missouri Distinguished Professor, Missouri University of Science and Technology)

Location: Ballroom E

Date: Thursday, January 30

Time: 12:00pm - 12:45pm

Track: 13. Modeling & Analysis of Interconnects, 07. Optimizing High-Speed Serial Design

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: Intermediate

Multi-layer PCBs designed for large ASIC packages have power vias adjacent to the signal vias to match the pin map of ASIC packages. Increase in near-end and far-end crosstalk (NEXT and FEXT) and resonance in insertion loss may result from coupling between signal vias and power vias. Root cause of the power via induced quasi-quarter-wavelength insertion loss resonance is explained in this paper for the first time. Different methods to mitigate the unwanted resonance and lower the crosstalk levels are proposed and verified using 3D full-wave simulation.

Takeaway

Power via induced quasi-quarter-wavelength resonance under ASIC pin field is explained for the first time.
A novel crosstalk reduction methods to eliminate power via induced quasi-quarter-wavelength resonance is proposed. The proposed methods can be used to guide PCB designer to minimize crosstalk under large ASIC packages.