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Analysis Through Simulation of High Speed DDR4 Link Failures Due to Via Stubs in the Channel

Benjamin Dannan (Principal Electrical Engineer Robotics, Diversey Inc.)

Location: Ballroom A

Date: Thursday, January 30

Time: 12:00pm - 12:45pm

Track: 07. Optimizing High-Speed Serial Design, 13. Modeling & Analysis of Interconnects

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

DDR4 requires tight specifications for high-speed operation and channel modeling requires high accuracy since design could operate close to the specification limits.The JEDEC standard defines the maximum speed for DDR4 as 3200 mega-transfers per second (MT/s), although the first DDR4 DIMMs just become available at those speeds. As PCBs continue to become more complex with higher densities, this is driving an increase in the number of layers in a PCB stackup used to ensure all signals in the design are routed effectively. Thick PCB vias with long stubs create unwanted resonances in the channel, if these resonances occur near the Nyquist frequency of the bit rate, they can devastate the eye opening at the receiver. The question is how big is the parasitic capacitance from this vias and will it have an adverse effect on the switching edge? The scope of this effort applies to understanding the impact of via stubs to the impedance of the signal lines on DDR4 memory. The goal of this research effort is to present ideas intended to see how far we can push a complex design using DDR4 with long via stubs in the channel. The intent of this effort is to prove with SI simulation at what via length DDR4 link failures will occur and correlate those results (with link failures) to the resonant frequency of the via created by the stub.