DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Early Bird Registration Now Open till November 30th. Save Up to $300 Today!

DesignCon 2019 Presentation Viewer

Purchase procecdings

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.

Analyzing LPDDR4X Interfaces using Circuit and Channel Simulation: A Case Study

Snehamay Sinha (Manager, System Co-design team, Processors Group, Texas Instruments)

Location: Great America 3

Date: Thursday, January 31

Time: 9:05am - 9:45am

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD

Cadence Design Systems

With the release of DDR4, memory interface analysis shifted from traditional setup/hold to a mask-based approach. This drove EDA tools to develop new post-processing and compliance checking techniques, along with new methodologies to go along with them. LPDDR4 reduced margins by dropping the associated supply voltage, and LPDDR4X exacerbates this even further, making power-aware SI analysis essential, impacting extraction and modeling methods. For high-reliability applications, it also becomes desirable to perform bit error rate (BER) analysis, further perturbating traditional approaches. TI will present some of the challenges they have faced in this new analysis world, and the methodologies they have adopted to address them.