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Architecture & Signaling Challenges & Solutions for the Next-Generation 112G Ultra Short (XSR) Electrical Interfaces Within a Package

Mike Li (Fellow, Intel)

Hsinho Wu (Designer Engineer, Intel Corp.)

Masashi Shimanouchi (Design Engineer, Intel)

Location: Ballroom D

Date: Thursday, January 31

Time: 10:00am - 10:45am

Track: 10. High-Speed Signal Processing, Equalization & Coding

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Introductory

Next-generation CEI-112G-XSR die-to-die (D2D) and die-to-OE (D2OE) electrical interfaces within the package (up to ~50 mm channel length and up to ~8-10 dB channel insertion loss (IL) at 28 GHz) are presently being specified within the Optical Internetworking Forum (OIF) in order to support development of 400G, 800G, and > 1T electro-optical systems based upon 1 to N channel 112 Gb/s serial interfaces, with PAM4 coding. This paper will investigate transmitter and receiver electrical, jitter, noise, signal-to-noise and distortion (SNDR), nonlinearity requirements, channel topology and characteristics, clocking and equalization, in order to meet the power, performance, latency, and compatibility objectives.


The audiences will be provided with transmitter (TX) and receiver (RX) equalization (EQ) and clocking, channel topology and characteristics required for PAM-4 signaling over the OIF's new 112 Gb/s ultra-short reach (XSR) die-to-die (D2D) and die-to-optical engine (D2OE) electrical interfaces within the package for integrated photonics with the lowest possible power.

Intended Audience

Basics on the jitter, noise, highs-speed I/Os.