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Boot Camp – Relating SI & PI for High-Speed Digital Boards: FPGA DDR4 Case Study

Jack Carrel  (Applications Engineer, Xilinx)

Steve Sandler  (Managing Director, Picotest)

Heidi Barnes  (Senior Application Engineer, Keysight)

Location: Ballroom G

Date: Tuesday, January 28

Time: 9:00am - 4:30pm

Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation

Format: Boot Camp

Pass Type: All-Access Pass, Alumni All-Access Pass, Boot Camp Pass - Get your pass now!

Vault Recording: TBD

Audience Level: Introductory

This power intergrity hands-on boot camp combines simulation and measurement. See how the gigabit SI world of IoT, automotive, cloud server products, etc. with the demand for lower power and multiple power rails is driving new paradigms for flat impedance and not just a maximum target Z. Start with understanding how to define a PDN impedance mask for a given load transient and package/die model. Learn how to build the behavioral model for a dc-dc converter so that both large switching transients as well as small signal load steps can be simulated when delivering power to a high-speed digital load. Step through optimizing the decoupling for an FPGA DDR4 example and then run the full PI eco-system simulation to look at the signal integrity when driven by a switching regulator power delivery network.

Note that this boot camp will break from 11:50 AM to 1:30 PM for the keynote and lunch.

Each section will include access to hands-on simulation using 1 of 40 supplied laptops or access to a cloud-based version using an attendee’s personal laptop. Measurement demo’s will also be included for the VRM modeling sections. The boot camp will be broken down into the following 5 sections:

  1. Evolutionary changes in Power Integrity that are driving reduced margins and the need to find the worst case power delivery network noise ripple. Understand the basics of flat impedance design to avoid the risk of rogue voltage waves and at the same time reduce component count. This is critical for high current power rails, low noise SERDES power rails, and high dynamic single ended switching for DDR memory.
  2. Power Integrity Z Mask and the regions of operation – Learn how to put together a realistic Z Mask for PDN design leveraging the information from the load transient and the package/die model.
  3. Simulating the Power Integrity Eco-system requires more than just an R-L model for the VRM. Learn how simple control loop state space models of dc-dc converters can be built from a few measurements to enable simulations of both small signal and large signal power rail transients. The resulting model also works for optimizing PSRR and exploring the loading of multiphase designs.
  4. Optimizing decoupling capacitors for flat impedance design requires the right models to enable simulation to measurement correlation. Understand the difference of Capacitor models with parasitics for use in SPICE like simulations, and without PCB mounting parasitics for use with EM models. Use the correct models to step through the process of estimating the required decoupling capacitance for flat impedance and then running a simulation optimizer to select the best combination of commercially available values.
  5. Utilize all the skills learned to design a flat impedance network for an FPGA and DDR4 design example. Analyze an existing design to find the worst case ripple load.

Intended Audience

Attendees should be familiar with power rail simulations (SPICE type), AC simulations with S-Parameter and Z-Parameters, PCB technology, capacitors, inductors, switch mode power supply basics, and low impedance 2-port shunt VNA measurements. (Bode plots are not a prerequisite)