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Building Better 2.5D/3DIC Packages
Jun So Pak (Pricipal Engineer, Foundry Samsung Foundry)
Location: Mission City M1
Date: Thursday, January 30
Time: 3:45pm - 4:25pm
Track: Sponsored Session
Vault Recording: TBD
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Multi-chip packages including 2.5D/3D stack IC are becoming the norm as engineers strive for designs with increased functional density, needed to differentiate their products in today’s market. To guide engineers designing advanced packages for 2.5D/3D stack IC, Samsung Foundry and Cadence have partnered to develop a 2.5D/3D design reference flow. This presentation outlines the Samsung Foundry’s MDI™ reference flow with emphasis on top-level design management, planning and optimization; along with automatic routing and electrical analysis of multi-chip designs. Also, this talk will introduce Samsung Foundry’s PI/SI design methodologies to implement such advanced package solutions for HPC/AI/Network applications.