DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Building Better 2.5D/3DIC Packages

Jun So Pak  (Pricipal Engineer, Foundry Samsung Foundry)

Location: Mission City M1

Date: Thursday, January 30

Time: 3:45pm - 4:25pm

Track: Sponsored Session

Vault Recording: TBD

Cadence Design Systems

Multi-chip packages including 2.5D/3D stack IC are becoming the norm as engineers strive for designs with increased functional density, needed to differentiate their products in today’s market. To guide engineers designing advanced packages for 2.5D/3D stack IC, Samsung Foundry and Cadence have partnered to develop a 2.5D/3D design reference flow. This presentation outlines the Samsung Foundry’s MDI™ reference flow with emphasis on top-level design management, planning and optimization; along with automatic routing and electrical analysis of multi-chip designs. Also, this talk will introduce Samsung Foundry’s PI/SI design methodologies to implement such advanced package solutions for HPC/AI/Network applications.