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Case Studies Isolating Types of Power Integrity Effects on Signal Integrity & Means of Mitigation

Nitin Bhagwath (Product Architect, Mentor, A Siemens Business)

Rula Bakleh (SI/PI Expert, Samtec Teraspeed Consulting)

Location: Ballroom F

Date: Wednesday, January 30

Time: 9:00am - 9:45am

Track: 02. Chip I/O & Functional Block Modeling & Validation Solutions, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Intermediate

The interaction between power and signal integrity is often complicated and confusing. With the single-ended DDR5 bus reaching the same data rates as many popular differential SerDes channels, a better understanding of this interaction becomes more crucial. In this paper we discuss the three primary methods that power and signal integrity interact with each other, and present multiple cases that demonstrate situations where such interactions occur, with a focus on the impact on DDR5.


The signal and power integrity interaction in parallel interfaces are becoming more of problem due to the elevate speeds (4266-6400 MT/s) required by DDR5 interfaces. This paper presents a comprehensive understanding of the primary interaction/issues in designing such interfaces. It also presents how to identify the sources of these interactions and how to mitigate them and/or alleviate them when/if they do occur.

Intended Audience

Some understanding of signal integrity, switching operation of parallel interface designs, and power distribution network (PDN) design.

Presentation Files