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Saman Sadr (VP, Product Marketing of IP Cores, Rambus)
Location: Great America 3
Date: Wednesday, January 29
Time: 11:05am - 11:45am
Track: Sponsored Session
Vault Recording: TBD
As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more complex system on chips (SoCs). This is particularly true at a time when the benefits of scaling have slowed or stopped altogether. Further, as the complexity of SOCs increases, so do the costs to manufacture in leading-edge FinFET geometries. Chip disaggregation, or chiplets, offers an alternative to the traditional monolithic SoC scaling approach. Aggregating multiple chiplets to perform the function of a single monolithic IC de-risks the overall system by reducing complexity and increasing yields. This session will cover the architectures and interface alternatives critical for chiplet implementations.