DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Chiplet Architecture Interface Alternatives

Saman Sadr  (VP, Product Marketing of IP Cores, Rambus)

Location: Great America 3

Date: Wednesday, January 29

Time: 11:05 am - 11:45 am

Track: Sponsored Session

Vault Recording: TBD

Rambus Inc

As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more complex system on chips (SoCs). This is particularly true at a time when the benefits of scaling have slowed or stopped altogether. Further, as the complexity of SOCs increases, so do the costs to manufacture in leading-edge FinFET geometries. Chip disaggregation, or chiplets, offers an alternative to the traditional monolithic SoC scaling approach. Aggregating multiple chiplets to perform the function of a single monolithic IC de-risks the overall system by reducing complexity and increasing yields. This session will cover the architectures and interface alternatives critical for chiplet implementations.