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James Church (Principal Design Engineer, Broadcom Incorporated)
Location: Room 203
Date: Wednesday, January 29
Time: 2:00pm - 2:40pm
Track: Sponsored Session
Vault Recording: TBD
As critical IP teams settle on disparate technology nodes, a chiplet architecture allows organizations to build up optimized platforms within a single packaged part.
The engineering cost of this optimization is adding additional complexity as chip-to-chip communication involves large numbers of simultaneously switching signals within a dense routing mesh which can be prohibitively hard to fully model. Maintaining a stable voltage supply involves validating the power distribution network over a large frequency spectrum as well as over a diverse and complex supply network including TSV's.
Modeling semiconductor channels and power supply networks provides a challenge to model extraction tool flows due to the semiconductor nature of the material, the differences in design methodologies, and the substantial differences in material technology files where process and temperature variation play a significant impact on performance.
This presentation will discuss a holistic approach to signal and power integrity for chip-to-chip (chiplet) analysis.