April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Speaker:
Vijay Kasturi ( Technical Lead Signal Integrity, Intel)
Author:
Hsinho Wu (Design Engineer, Intel)
Location: Ballroom D
Date: Thursday, April 7
Time: 11:15 am - 12:00 pm
Track: 02. Chip I/O & Power Modeling
Format: Technical Session
Education Level: Advanced
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: Advanced
Channel Operating Margin (COM) has become the standard channel and transceiver compliance test method since 2014 (IEEE 802.325Gbps Ethernet). It has since evolved with increasing data rates, complexities, and utilizations in the areas of device capabilities and associated stress and compliance tests. IBIS-AMI is the de-facto device modeling format for transceivers and it is used to emulate realistic device behaviors and estimate link margins. In this paper, we will demonstrate a COM based IBIS-AMI model development and illustrate link level performance correlation to 106G Ethernet and 112Gbps OIF-CEI COM with various reference channels. COM based IBIS-AMI can enable system designers to ensure system compliance and study the impacts from non-linear effects like jitter, noise, and link adaptions. Device vendors can seamlessly switch between design vs spec models to verify the compliance of their transceivers.
System and IP design leveraging COM based IBIS-AMI
Familiarity with COM, IBIS-AMI and Ethernet standards