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Hsinho Wu (Design Engineer, Intel Corp)
Mike Li (Fellow, Intel Corp)
Masashi Shimanouchi (Design Engineer, Intel Corp)
Location: Ballroom D
Date: Thursday, January 30
Time: 2:50pm - 3:30pm
Track: 09. High-Speed Signal Processing, Equalization & Coding, 07. Optimizing High-Speed Serial Design
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
IEEE 802.3 Ethernet and OIF-CEI are working aggressively on the next data rates: 106Gbps and 112Gbps. The standards bodies studied and surveyed the transceiver technologies and channel needs/limitations while continuing the use of Channel Operating Margin methodology. In this paper, we will summarize the specification development and the findings of the upcoming 106/112Gbps long-reach and chip-to-chip link standards. Specifically, we will focus on the development of baseline transmitter and receiver specifications which describe characteristics such as electrical performance/limitations, packages, and equalization capabilities. The study will also highlight how the standards achieve these goals while optimizing convoluted performance and cost matrix.
The audience will gain the knowledge on upcoming IEEE 802.3 106Gbps Ethernet and OIF CEI 112Gbps long-reach and chip-to-chip specifications as well as insights in link designs optimizations.
For audience with knowledge on high-speed serial links, jitter and noise components, and equalization schemes in serial communication links.