Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.
Location: Ballroom C
Date: Thursday, January 30
Time: 9:00am - 9:45am
Track: 13. Modeling & Analysis of Interconnects, 07. Optimizing High-Speed Serial Design
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
Crosstalk and return loss become more prominent as SerDes link speed increases and moves from NRZ to PAM4, e.g. for CEI or PCIe Gen5/6. Their budgets are well defined in the end-to-end channel but are lacking in each section for individual channel components. S-parameters of all components with different losses are cascaded to capture the complicated interactions of the multi-sectional attenuation, coupling, and reflections. Each section's impact on the overall budgets and channel margins are studied and compared in different link topology scenarios. Generalized design trade-offs of sectional crosstalk and return loss are made for best link performance with constraints.
Crosstalk, return loss budget and the trade-offs for each section in a SerDes channel are studied with S-parameters cascaded. Complicated interactions of attenuation, coupling, and reflections from different components are simplified to understand the individual sectional impact on overall channel margin. Design trade-offs are made for different link topologies.