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Adam Gregory (Signal Integrity Engineer, Samtec)
Istvan Novak (Signal Integrity Engineer, Samtec)
Clement Luk (Signal Integrity Engineer, Samtec)
Gustavo Blando (Signal Integrity Engineer, Samtec)
Gary Biddle (SI/EMI Development Engineer, Samtec)
Location: Ballroom G
Date: Wednesday, January 29
Time: 2:50pm - 3:30pm
Track: 10. Power Integrity in Power Distribution Networks, 13. Modeling & Analysis of Interconnects
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
This paper will analyze the frequency dependent resistance and inductance of power connector pin patterns. The details of a single power pin will be analyzed, and the final results will come from parametric studies of pin arrays that are part of specific printed circuit board layouts. The results of this study will have 2 significant outcomes to the designer utilizing a power connector. 1) A layout that minimizes individual power pin current will minimize system power consumption. 2) An accurate representation of frequency dependent resistance and inductance can be used to strategically optimize signal-to-power pin isolation to reduce noise.
Layered metal in power connector pins impact low and high frequency inductance and resistance differently. Current distribution and noise coupling varies with pin assignment and layout of connected boards.