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Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

DARPA Organic Interposer Characterization

Dylan Williams  (Electrical Engineer, NIST)

Jerome Cheron  (Electrical Engineer, NIST)

Richard Chamberlin  (Electrical Engineer, NIST)

Brent Devetter  (Senior Engineer, Boeing)

Sam Chitwood  (Engineer, Cadence Design Systems)

Ken Willis  (Product Engineering Architect, Cadence)

Brad Butler  (Application Engineer, Cadence Design Systems)

Farhang Yazdani  (President & CEO, Broadpak Corp.)

Location: Ballroom G

Date: Thursday, January 30

Time: 11:00am - 11:45am

Track: 13. Modeling & Analysis of Interconnects, 12. Applying Test & Measurement Methodology

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: Intermediate

Large, monolithic ICs are being replace by an array of chiplets in wide ranging applications of our industry. A few high-profile examples are Intel's "foveros", EMIB interposers, and AMD's latest Ryzen processors. Chiplet-to-chiplet interconnects of single- and sub-micron widths are a new challenge for designers to analyze and implement successfully. The U.S. Defense Advanced Research Projects Agency (DARPA) commissioned a project for two different interposers to be designed and built. The interconnects were measured with state-of-the-art methods developed at NIST, simulated and correlated. The methodology and results of this project will be shared with the industry at DesignCon 2020.


Chiplet-to-chiplet interconnects are a new challenge for designers to analyze and implement successfully. Build-up and silicon interposers have demonstrable tradeoffs of cost, performance, and design considerations. Measurement-to-simulation correlation results will be presented for interconnects and PDNs up to 110 GHz bandwidth.

Intended Audience

A cursory understanding of S-parameters, PDN impedance, material properties, interconnect behavior, VNA measurement equipment and methodology.

Presentation File