April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
DDR4-3200 FPGA-based System with Interposer Power Aware SI Simulation to Measurement Correlation
Speakers:
Benjamin Dannan (Staff Digital Engineer, Northrop Grumman)
Randy White (Memory Solutions Program Manager, Keysight Technologies)
Authors:
Hermann Ruckerbauer (Owner, Eye Know How)
HeeSoo Lee (DDR/SerDes Product Owner, Keysight Technologies)
Location: Ballroom E
Date: Wednesday, April 6
Time: 9:00 am - 9:45 am
Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation, 08. Measurement & Simulation Techniques for Analyzing Jitter, Noise & BER
Format: Technical Session
Theme : High-speed Communications
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
DDR4-3200 Simultaneous Switching Output (SSO) channel modeling is further challenged to ensure data (DQ) compliance specification for an eye opening at an ultra-low 1E-16 BER. As DDR4-3200 edge rates approach <100 ps, power aware SI simulation is necessary to achieve higher fidelity modeling. The intent of this paper is to present methods for creating accurate power aware signal integrity simulation which will demonstrate measurement correlation on the first DDR4-3200 FPGA memory controller, the Xilinx Versal, interfaced to a UDIMM with an interposer present during measurement.
This effort will combine simulation and measurement to show how to improve design margins during DDR4-3200 development cycles. Additionally, considerations and recommendations are provided for higher speed DDR5 designs with more complex power distribution, channel topologies and receiver architectures.
Takeaway
Key Takeaways:
To validate design performance on one of the first DDR4-3200 FPGA memory controllers as well as verify this design's electrical performance meets the JEDEC specifications through power aware simulations and measurements. These power aware simulations will look at the effects of SSN/SSO, while including the effects of probe loading and the interposer that is present during the measurement.
This effort will look at EM extracted models from a 3D solver and show considerations to properly simulate with these models. While concluding with actual measurement correlation being done on the same simulated DDR4-3200 model.
