DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Welcome to the DesignCon 2020 agenda and presentation download site. Here you can view and download conference and/or Chiphead Theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, it is likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

DDR5/LPDDR5 Design, Debug, Probing, and Validation Challenges and Solutions

Jennie Grosslight  (Memory Protocol Solutions Manager, Keysight Technologies)

Stephen Slater  (High-Speed Digital Simulation Product Manager, Keysight Technologies)

Stephanie Rubalcava  (R&D Solution Architect and Developer)

Location: Great America 1

Date: Wednesday, January 29

Time: 8:30am - 9:10am

Track: Keysight Education Forum

Vault Recording: TBD

DDR5 and LPDDR5 memory technologies will increase system data rates to 6400Mb/s and possibly higher. New design, debug, and validation challenges arise from higher data rates, DFE (decision feedback equalization), dynamic speed changes, power saving features, and lower voltage swings. Learn the latest test and measurement techniques to overcome DDR5 and LPDDR5 challenges.