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DesignCon 2020 Schedule Builder


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DDR5/LPDDR5 Design, Debug, Probing, and Validation Challenges and Solutions

Jennie Grosslight  (Memory Protocol Solutions Manager, Keysight Technologies)

Stephen Slater  (High-Speed Digital Simulation Product Manager, Keysight Technologies)

Stephanie Rubalcava  (R&D Solution Architect and Developer)

Location: Great America 1

Date: Wednesday, January 29

Time: 8:30am - 9:10am

Track: Keysight Education Forum

Vault Recording: TBD

DDR5 and LPDDR5 memory technologies will increase system data rates to 6400Mb/s and possibly higher. New design, debug, and validation challenges arise from higher data rates, DFE (decision feedback equalization), dynamic speed changes, power saving features, and lower voltage swings. Learn the latest test and measurement techniques to overcome DDR5 and LPDDR5 challenges.