DesignCon 2022 Schedule Builder

Recently, due to applications such as AI, 5G, cloud system, the demand of high performance hardware devices are increasing. However, high speed signaling can be distorted by signal integrity (SI) issues, which limits the bandwidth of channels of electrical devices. Equalization has been focused as a key technology to mitigate the SI issues. The hybrid equalizer, which has both active and passive components, is a powerful solution in that it can take advantages of both the active and passive equalizer. we propose a novel deep reinforcement learning (DRL)-based optimization method for designing a hybrid equalizer when a channel with arbitrary dimension is provided.

For verification, we apply our method to a hybrid equalizer design for the memory channel in the active silicon interposer of high bandwidth memory (HBM). The target hybrid equalizer consists of a continuous time linear equalizer (CTLE) and a passive equalizer. The goal is to optimize the transfer function of a single-ended CTLE and circuit parameters and placement of the passive equalizer simultaneously. Experimental results shows that the proposed method significantly outperforms conventional optimization method.

Takeaway

We propose a novel deep reinforcement learning (DRL)-based optimization method for designing a hybrid equalizer when a channel with arbitrary dimension is provided. By experimental results, our methodology, which is re-usable, outperforms conventional optimization method in terms of eye-contour.

Intended Audience

We propose a novel deep reinforcement learning (DRL)-based optimization method for designing a hybrid equalizer when a channel with arbitrary dimension is provided. By experimental results, our methodology, which is re-usable, outperforms conventional optimization method in terms of eye-contour.