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Delivering 100-Gbps Solutions for Chip to Module & Direct Attach Cable Implementations

Bruce Champion (Signal Integrity Engineer, TE Connectivity)

Nathan Tracy (Technologist, OIF VP of Marketing, TE Connectivity)

Location: Ballroom F

Date: Thursday, January 31

Time: 2:00pm - 2:40pm

Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Efforts are underway to define 100Gbps channels to support simpler, lower cost versions of 100G, 200G, and 400G Ethernet as well as enable 800G Ethernet links. This paper sets out to design, build, and test a C2M and various DAC configurations to give concrete evidence on what system designers can expect going forward for 100Gbps channels. The paper will include details of the analyzed channel impairments that needed to be addressed and some of the methodologies employed to develop a sound solution that can support these next generation physical solutions for the channel, connectors, and cables.

Takeaway

100Gbps C2M and DAC channels can reliably be achieved if certain considerations are taken into account in regards to channels, connectors, and cables.

Presentation Files

SLIDES_04_Delivering100GbpsSolutionsforChip_Champion.pdf
PAPER_04_Delivering100GbpsSolutionsforChip_Champion.pdf