DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Early Bird Registration Now Open till November 30th. Save Up to $300 Today!

DesignCon 2019 Presentation Viewer

Purchase procecdings

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.

Design & Development of DDR5 IBIS-AMI Models

Douglas Burns (Vice President/Director of Support & Consulting Services, SiSoft (Signal Integrity Software, Inc.))

Justin Butterfield (Senior Engineer: Silicon Signal Integrity, Micron Technology Inc.)

Randy Wolff (Principal Engineer, Silicon Signal Integrity Lead, Micron Technology Inc.)

Walter Katz (Chief Scientist, Signal Integrity Software Inc. (SiSoft))

Location: Mission City M1

Date: Wednesday, January 30

Time: 11:05am - 11:45am

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD


DDR5 is the next generation of high-speed DDRx memories expected to double the bandwidth of DDR4. To achieve these dramatic speed improvements, both controller and memory IO will need to adopt various equalization capabilities. These new features have required the model providers to adopt the capabilities of IBIS-AMI to properly model both the analog and equalization characteristics of the interface. This presentation will highlight key technology changes between DDR4 and DDR5, discuss the modeling environment requirements for time domain analysis, statistical analysis, and design regression, and finally describe the actual design and generation of IBIS-AMI DDR5 models.