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Design of 2.5D Interposer in High Bandwidth Memory & Through Silicon Via for High Speed Signal

Bo Pu (Staff Engineer, Samsung Electronics)

Location: Ballroom A

Date: Wednesday, January 30

Time: 10:00am - 10:45am

Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

The 2.5D interposer becomes a crucial solution to realize grand bandwidth of HBM for the increasing data requirement of HPC and AI applications. To overcome high speed switching bottleneck caused by the large resistive and capacitive characteristics of interposer, design methods to achieve an optimized performance in a limited routing area are proposed. Unlike the conventional single TSV, considering the reliability, multiple TSV are used as the robust 3D interconnects for each signal path. An equivalent model to accurately describe the electrical characteristics of the multiple TSV, and a configuration pattern strategy of TSV to mitigate crosstalk are also proposed.

Takeaway

A design method to achieve a high performance 2.5D interposer of high bandwidth memory is presented in this paper, and a model of the unconventional grouped TSV in signal integrity view is also proposed. Those methods could be practical guidelines for high speed signal design in 2.5D/3D interconnects and interposer.

Presentation Files

SLIDES_01_Designof2.pdf
SLIDES_01_Designof2.pdf
PAPER_Track_01_Design_of_2.pdf
SLIDES_01_Designof2.pdf
PAPER_01_Designof2.pdf