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Daniel Wu (Prinicpal Engineer, Xilinx Inc)
Valery Kugel (Sr. Distinguished Engineer, Juniper Networks)
Geoffrey Zhang (Distinguished Engineer and Supervisor of Transceiver Architecture and Modeling Team, Xilinx Inc)
Location: Ballroom B
Date: Wednesday, January 29
Time: 11:00am - 11:45am
Track: 09. High-Speed Signal Processing, Equalization & Coding, 07. Optimizing High-Speed Serial Design
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
CEI-112G-XSR-PAM4 specifies a 112 Gbps D2OE and D2D PAM4 electrical interface for SIP applications. Although XSR channels are low loss, the problem is shifted to dealing with reflections with limited power allowance. The current CEI suggested equalization is very challenging to meet the BER<1E-9 over PVT. This paper introduces THP for XSR SerDes with improved performance and reduced power. XSR channel modeling and s-parameters generation for a 10mm and 50mm package substrate traces. TX and RX T-coil architecture is adopted to further improve the link performance. THP working principle, with and without modulo operations, is elaborated, with case studies.
1. Basic concept high speed serial link systems, including transmitter, channel, and receiver
2. Basic understanding system performance evaluation and analysis
3. Basic knowledge of channel s-parameter description, including insertion loss, return loss, crosstalk, etc.
4. Basic idea of PAM4 signaling and its relationship with NRZ signaling