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Design Space Exploration with Polynomial Chaos Surrogate Models for Analyzing Large System Designs

Majid Ahadi Dolatsara (Student, Georgia Institute of Technology)

Ambrish Varma (Senior Principal Software Engineer, Cadence Design Systems)

Kumar Keshavan (Senior Software Architect, Cadence)

Madhavan Swaminathan (Professor, Georgia Institute of Technology)

Location: Ballroom B

Date: Wednesday, January 30

Time: 9:00am - 9:45am

Track: 15. Machine Learning for Microelectronics, Signaling & System Design, 04. System Co-Design: Modeling, Simulation & Measurement Validation

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Design of modern high-speed systems such as memories involves adjusting many parameters, which can be a tedious task. Designers might sweep the entire design space to find the desirable values, which is very time consuming. This paper proposes development of an accurate surrogate model based on the Polynomial Chaos theory, that includes sensitivity analysis, dimension reduction and a novel adaptive technique to distribute the training samples based on variations of the output. The generated surrogate model is used for design space exploration and statistical analysis. A DDR4 topology has been modeled by this approach which provided desirable results.


This paper discusses steps to develop a surrogate model for a complex high-speed system based on the polynomial chaos expansion. Because of fast training and evaluation processes, this model can be used for efficient analysis of the design space with negligible loss in accuracy.

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