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Location: Ballroom A
Date: Wednesday, January 29
Time: 2:00pm - 2:40pm
Track: 05. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: Intermediate
In 2013, even before DDR4 is widely used in mainstream designs, DDR5 standard was announced. Though the final version of DDR5/LPDDR5 standard is not available yet to the industry, the key features in DDR5 is known to public over the years: DDR5 would provide twice as wide bandwidth as DDR4 RAM does and with more efficient power management. In details, DDR5 interface design requires bus-based channel simulations to account for SSN and crosstalk comprehensively, with advanced modeling technologies for the filter methods employed in controller and memory designs. This paper presents major design challenges and solutions for LPDDR5 interface designs at system level. Modeling and simulation methods are demonstrated, and analysis tips will be shared with the industry.
LPDDR 5 interface design posts new challenges for designers to analyze and implement. A fully functional system with LPDDR5 interface can be achieved by understanding its key requirements and by choosing proper simulation and modeling methodologies.
A cursory understanding of DDRx designs, time domain circuit simulation and channel simulation, filter techniques of FFE/CTLE/DFE, and IBIS-AMI modeling.