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Ravindra Rudraraju (Director
Richard Allred (Signal Integrity Expert, Mathworks)
Barry Katz (RF and Analog Mixed Signal Manager, Mathworks)
Jonggab Kil (Lead
Tripp Worrell (SerDes Manager, Mathworks)
Walter Katz (Signal Integrity Expert, Mathworks)
Vijay Kasturi (SI/PI Engineer, Intel)
Location: Ballroom E
Date: Wednesday, January 29
Time: 9:00am - 9:45am
Track: 02. Chip I/O & Power Modeling & Validation Solutions, 07. Optimizing High-Speed Serial Design
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
Today's high speed SerDes design requires upfront effort by architects to allow for the direct extraction of an IBIS-AMI model from the architectural model. We demonstrate a process of creating an IBIS-AMI model from detailed characterization data of the CTLE, DFE and CDR. The multi-stage CTLE is defined by frequency domain curves and saturating voltage in/out tables; poles/zeros extracted from the curves by vector fitting are combined with a memoryless non-linearity to model each CTLE stage. Advanced impulse response equalization adaptation schemes quickly finds near optimum settings and serve as a starting point for custom adaptation implementations.
Demonstrates a Design for AMI model workflow that will enable SerDes architects to create an IBIS-AMI model from their detailed architectural designs. Detailed characterization and modeling of the CTLE, DFE and CDR. Advanced equalization adaptation schemes that are readily modified by users.
Basic knowledge of a SerDes system