DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Early Bird Registration Now Open till November 30th. Save Up to $300 Today!


DesignCon 2019 Presentation Viewer

Purchase procecdings

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.

DFE Implementation & Optimization Considerations for Test & Measurement

Kalev Sepp (Signal Integrity Consultant for VESA, Sepson Analytics LLC)

Location: Ballroom A

Date: Wednesday, January 30

Time: 2:00pm - 2:40pm

Track: 13. Applying Test & Measurement Methodology, 09. Measurement, Simulation & Optimization of Jitter, Noise & Timing to Minimize Errors

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Intermediate

As the speed of serial data links increases, the decision feedback equalizer (DFE) becomes a standard component in design and measurement methodology of such links. Differences in behavioral DFE application can complicate transmitter and receiver characterization and pass/fail testing as well as correlation between different measurement solutions. The talk focuses on practical behavioral DFE implementation details that are encountered in signal integrity analysis. An efficient DFE tap optimization and eye rendering algorithms are presented. Additionally, jitter, eye width and height measurements after DFE are discussed.

Takeaway

Understand different interpretations of decision feedback operation in test and measurement system when evaluating signals with closed or nearly-closed eyes. Jitter and eye measurements can have different meaning depending on actual hardware and software implementation. Learn about various trade-offs in optimization of DFE parameters and how to face correlation challenges.

Intended Audience

Audience with general understanding of serial data links and receiver equalization, signal integrity, CTLE and DFE functions, equalizer optimization, adaptation, and real-time oscilloscope functionality.

Presentation Files

SLIDES_13_DFEOptimizationAndImplementationConsiderations_Sepp.pdf
PAPER_13_DFEImplementationOptimizationConsiderations_Sepp.pdf