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Karthik Chandrasekar (Signal/power integrity engineer, Seagate)
Emmanuel Atta (Signal integrity engineer, Seagate)
Pritesh Pawaskar (Power integrity engineer, Seagate Technology)
Location: Ballroom F
Date: Thursday, January 30
Time: 11:00am - 11:45am
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 10. Power Integrity in Power Distribution Networks
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
Noise coupling between analog/digital blocks on the chip is a key issue for SI/PI engineers to analyze typically and is a key factor in deciding ground plane sharing/isolation on the die, package and PCB to meet performance specs. While it is possible to conservatively isolate ground planes to mitigate noise coupling to meet performance specs it adds to system cost in terms of BGA pin count and number of routing layers. In this work we discuss EDA flow based approaches to model analog/digital coupling at a system level to help practicing engineers in making the right tradeoff for their design
In this work we discuss EDA flow based approaches to model analog/digital coupling at a system level to help practicing engineers in making the right tradeoff for their design. We go through case studies of real issues we have encountered and validate the simulation approaches discussed qualitatively with measurements
Working knowledge of signal/power integrity