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EDA Tool-Based Methodology for Accurate Extraction ofOn-Die Capacitance & Resistance

Karthik Chandrasekar (Sr. SI/PI Engineer, Intel PSG)

Guang Chen (Sr. SI/PI Engineer, Intel)

Wendem Beyene (Principal Engineer, Intel PSG)

Shaan Awasthi (CAD manager, Intel PSG)

Anil Gundurao (CAD Engineer, Intel)

Ying Fei Tan (Package engineer, Intel PSG)

Location: Ballroom E

Date: Thursday, January 31

Time: 2:50pm - 3:30pm

Track: 11. Power Integrity in Power Distribution Networks, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

On-die capacitance (ODC) is important in the design of robust power distribution network (PDN) by providing a means to minimizing the high-frequency PDN impedance. ODC is critical to mitigate high-frequency noise when other types of decoupling capacitance cannot provide necessary charge. It is challenging, however, to predict ODC accurately at full-chip level where various types of ODC including intrinsic gate capacitance and signal interconnect capacitance are a significant contributor. This work provides insights to power integrity engineers in determining ODC more accurately at different stages of the design with minor adaptations to existing CAD flows, leveraging industry standard tools.

Takeaway

This work provides insight to the practicing power integrity engineers in determining On-Die Capacitance (ODC) for different applications more accurately at different stages of a product design cycle with minor adaptations to existing CAD flows leveraging industry standard tools as well as practical wisdom in avoiding common pitfalls.

Intended Audience

Basic knowledge of PDN design

Presentation Files

SLIDES_11_EDAToolBasedMethodologyfor__Chandrasekar.pdf
PAPER_11_EDAToolBasedMethodologyfor_Chandrasekar.pdf