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Effect of PCB Fabrication Variations on Interconnect Loss, Delay, Impedance & Identified Material Models for 56-Gbps Interconnect Designs

Yuriy Shlepnev (President and Founder, Simberian Inc.)

Alex Manukovsky (Technical Lead, SI/PI Team, Intel)

Location: Ballroom G

Date: Wednesday, January 30

Time: 10:00am - 10:45am

Track: 14. Modeling & Analysis of Interconnects

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

This paper is the first attempt to separate variations of PCB interconnect geometry and identified material model parameters with the goal to build reliable models for analysis of 56 Gbps PAM-4 links. Test structures were put on the same panels with the production boards. S-parameters for four batches were measured up to 40-70 GHz. The structures were cross-sectioned, to investigate the geometry variations. Variations of impedances, phase delays and losses as well as identified dielectric and conductor roughness model parameters are observed and reported. This is one more step toward the design of predictable PCB interconnects.


Design of predictable PCB interconnects for 56 Gbps PAM-4 data links. Learn how to pre-qualify your next PCB manufacturer . Learn how to separate geometrical variations from the dielectric and conductor roughness models, how to identify the dielectric and conductor roughness models with the separation of the losses. Learn how to select the measurement equipment for measurements from 1 MHz up to 40-50 GHz for PCB properties identification .

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