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Effect of Power Plane Inductance on Power Delivery Networks

Shirin Farrahi (Principal Software Engineer, Cadence Design Systems)

Mehdi Mechaik (Staff Application Engineer, Cadence Design Systems)

Ethan Koether (Hardware Engineer, Oracle)

Istvan Novak (Samtec)

Location: Ballroom E

Date: Wednesday, January 30

Time: 9:00am - 9:45am

Track: 11. Power Integrity in Power Distribution Networks, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

Power plane loop inductance is an important metric in Power Delivery Network (PDN) design, but it is not easy to visualize how PCB design changes impact a power plane's loop inductance. This paper considers the impact on loop inductance of common power plane design changes such as the placement of vias, the anti-pad pitch and periodicity in a pin field array, and the placement of decoupling capacitors. The analysis considers tradeoffs of parametric values and provides guidance to engineers for PDN designs that meet a desired frequency response, minimize ground bounce, and reduce coupling due to power plane loop inductance.


This paper considers design tradeoffs that impact power plane loop inductance including changes to vias, anti-pads, and decoupling capacitors. Knowledge of these tradeoffs will help engineers understand how PCB design changes will impact a power plane's loop inductance and ultimately help them achieve robust electrical performance.

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