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April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Se-Jung Moon (IO architect, Intel)
Beomtaek Lee (Senior Principal Engineer, Intel)
Xinjun Zhang (Technical Lead, Intel)
Jianting Li (Analog Engineer, Intel)
Jong-Ru Guo (Analog Engineer, Intel)
Location: Ballroom G
Date: Thursday, April 7
Time: 2:00 pm - 2:45 pm
Track: 13. Modeling & Analysis of Interconnects, 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Format: Technical Session
Theme : Infrastructure
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
In the high-speed differential (HSD) interface design, the intra-pair skew becomes more critical as the link speed is ever increasing beyond 56Gbps+ signaling. The skew within a differential pair (intra-pair skew) deteriorates eye opening at the receiver and degrades the channel performance significantly in HSD signaling. However, industry lacks and accurate and stable intra-pair skew measurement methodology, which created a significant gap in interconnect testing and qualification. Also, directive and comprehensive intra-pair skew modeling is not available, the risk assessment of the skew over the channel performance cannot be well explored. In this paper, we will first start with introduction to the intra-pair skew modeling method. Then, the effective intra-pair skew (EIPS) is presented, which is directly calculated from S-parameter data as a single value without time-domain conversion.
We used a comprehensive frequency domain method to model and quantify the intra-pair skew for direct assessment of the skew impact on the channel performance and accurate and effective characterization.