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Electrical Integrity for LPDDR5 Memory Technology

Vishram Pandit (Platform Architect, Intel Technology India Pvt. Ltd)

Aiswarya Pious (System Architect, Intel Corporation)

Prabhat Ranjan (Intel Technology)

Arvindh Rajasekaran (Analog Engineer, Intel)

Kirankumar Kamisetty (Senior Analog Engineer , Intel, Oregon USA)

Jun Liao (Technical Lead for Memory Subsystem Electrical Design , Intel Hillsboro)

Nagi Aboulenein (Lead Client Memory System Architect )

Christopher Cox (Memory Design Architect , Intel Folsom)

Location: Ballroom B

Date: Wednesday, January 30

Time: 10:00am - 10:45am

Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Intermediate

LPDDR5 is an emerging memory technology for Low Power small form factor electronic design systems. LPDDR power delivery operating range is getting reduced in subsequent generations. Also, the signal integrity requirements are getting stringent as the speeds of the operation are increasing. It is becoming challenging to system design engineers to comply to the JEDEC specifications. In this paper we describe the specification trends and various techniques that can be used to meet electrical requirements including power integrity, signal integrity, thermal integrity, power and performance.


This paper describes LPDDR5 memory technologies constraints for Power Delivery, Power Integrity, Power and performance, Thermal, and explains system/platform design recommendations to meet those requirements.

Intended Audience

Basic understanding of memory technologies, power integrity, and signal integrity

Presentation Files