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Elimination of Highly Reflective Structures Through Sliding Decision Feedback Equalization

Joseph Aday (Principal Electrical Engineer, Raytheon)

Juli Olenick (Senior Electrical Engineer, Raytheon)

Torstein Molvik (Principal Electrical Engineer, Raytheon)

Hannah Lee (Senior Electrical Engineer, Raytheon)

Carolyn Henry (Senior Electrical Engineer, Raytheon)

Geoff Zhang (Distinguished Engineer and Supervisor, Xilinx)

Hongtao Zhang (Senior Staff Design Engineer, Xilinx)

Location: Ballroom F

Date: Wednesday, January 30

Time: 11:00am - 11:45am

Track: 04. System Co-Design: Modeling, Simulation & Measurement Validation, 10. High-Speed Signal Processing, Equalization & Coding

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Intermediate

Return-loss dominated high speed channels are not uncommon within the sectors of aerospace, defense, drilling, medical, and space, which require high-reliability products. In these environments, critical mechanical requirements can push electrical performance into a very challenging corner. Conventional SerDes put lots of emphasis on channel ISI equalization and somewhat in mitigating the impact of crosstalk, while leaving serious reflections to channel designers. This paper revisits the concept of the Sliding Tap DFE (ST-DFE), and proves it's applicability in high-reliability system-level solutions. We conclude with an example of a difficult impairment that is critical to product success, and its resolution.


Return-loss dominated high speed channels are not uncommon with high-reliability products. SerDes solutions with ST-DFE is of great importance in providing a system level optimal solution with excellent performance margin and great reliability. The working mechanism of the ST-DFE is discussed. A real product example with an ST-DFE is provided.

Intended Audience

1. Basic knowledge of channel impairments and channel equalization
2. Basic idea of DFE working principle
3. Basic concept of link margin analysis

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