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Enable Innovation with Hardware-Enforced Security at the Core

Ben Levine (Senior Director of Product Management, Rambus)

Location: Great America 3

Date: Wednesday, January 30

Time: 11:05am - 11:45am

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD


Making a highly complex processor optimized for performance, into a secure processor is very difficult. Instead, move security-sensitive code into secure hardware cores siloed from general purpose processors, so the cores can utilize processors optimized for secure operation and implement hardware protection against attacks. See an example of a secure core implemented using a custom-designed RISC-V CPU targeted specifically for security; demonstrating a layered security approach offering robust protection against a broad range of threats through carefully thought out system design.