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Enabling 6.4-Gbps/pin LPDDR5 Interface Using Bandwidth Improvement Techniques

Billy Koo (Principal Engineer, Samsung Electronics)

Location: Ballroom D

Date: Thursday, January 31

Time: 9:00am - 9:45am

Track: 07. Advanced I/O Interface Design for Memory & 2.5D/3D/SiP Integrations

Session Type: Technical Session

Vault Recording: TBD

Audience Level: All

New applications such as artificial intelligence, autonomous cars, high performance computing, and embedded vision are driving stricter requirements for memory performance and power efficiency. These demands led the new mobile DRAM technology evolved to the fifth generation (LPDDR5). LPDDR5 delivers significant reduction in power and extremely high bandwidth as compared to LPDDR4. In this paper, we present various bandwidth improvement techniques which enable world's first 6.4 Gbps/pin LPDDR5 interface. The achieved READ and WRITE valid window margins(VWM) at 6.4 Gbps are 0.36 UI and 0.4 UI, respectively. The measured WCK clock duty was within 43~57% at 3.2 GHz including process variation and peak-to-peak periodic jitter was less than 20ps. Also various measured results will be shown as enabling references for other LPDDR5 interface designers


To achieve over 6.4 Gbps interface speed, ISI minimized tunable equalizer scheme which can support either de-emphasis or pre-emphasis is used in driver side. And also power-efficient CTLE is adopted in receiver side. Area optimized per bit offset calibration scheme is used to improve each bit's READ valid window margin.

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