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Enabling IBIS-AMI Simulations for Systems Containing PAM4 Retimers at 112 Gbps

Fangyi Rao (Master Engineer, Keysight Technologies)

Hongtao Zhang (Senior Staff Design Engineer, Xilinx)

Geoff Zhang (Distinguished Engineer and Supervisor, Xilinx)

Location: Ballroom D

Date: Wednesday, January 30

Time: 10:00am - 10:45am

Track: 08. Optimizing High-Speed Serial Design, 04. System Co-Design: Modeling, Simulation & Measurement Validation

Session Type: Technical Session

Vault Recording: TBD

Audience Level: Intermediate

End-to-end system simulations of PAM4 channels with retimer are
required in 112G C2M and VSR link analyses. In this paper we
present a novel AMI-repeater-based modeling approach for
PAM4 retimer that enables full link simulation of retimer
PAM4 channels. Equalization, CDR, data recovery and jitter
transfer characteristics of PAM4 retimer can be captured
accurately in this approach. Simulation results of 112G PAM4
channels demonstrate that the proposed method provides more
reliable system performance predictions compared to the
traditional practice which simulates each channel section
independently.

Takeaway

AMI modeling with retimers and end-to-end link simulations for PAM4 is still unexploited. This paper shows that simulations within each section is different from the true end-to-end simulations. The paper also discusses what it takes to enable such simulations from both device modeling and EDA tool processing perspective.

Intended Audience

1. Basic idea of NRZ and PAM4 signaling
2. Basic concept of retimers and its impact on the link
3. Basic knowledge of IBIS-AMI modeling for high speed SerDes
4. Basic understanding of system level end-to-end simulations

Presentation Files

PAPER_08_EnablingIBISAMISimulationsForSystems_Rao.pdf
SLIDES_08_EnablingIBISAMISimulationsForSystems_Rao.pdf