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Amanda (Xiaoqing) Dong (SerDes design engineer, Xilinx)
Nick (Chunxing) Huang (SI design engineer, Shenzhen Zhongzeling Electronics)
Geoff (Geoffrey) Zhang (distinguished engineer, Xilinx)
Location: Ballroom C
Date: Wednesday, January 29
Time: 2:00pm - 2:45pm
Track: 09. High-Speed Signal Processing, Equalization & Coding, 08. Measurement, Simulation & Improving Jitter, Noise & BER (Pre & Post FEC)
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: Intermediate
FEC becomes indispensable for 56G-PAM4 link systems. In a multi-part-link-system where FEC is only used in end devices, mixed mode errors from each link section collectively impact the final stage FEC performance.
We introduce a simulation algorithmic model for evaluating an end-to-end PAM4 RS-FEC for multi-part link applications. FEC symbol error patterns within each section are combined to form FEC symbol error patterns for analyzing the final stage FEC capability.
The goal of the paper is to provide a method for end-to-end FEC performance evaluation and to help with system insertion loss budgeting to achieve the overall best link margin.
An engineering method for multi-part link end-to-end FEC performance analysis is proposed. The new method provides burst error signatures and BER for each section and their impact on the overall link FEC performance. Doing so allows system engineers to budget link loss for multi-part systems to achieve optimal system performance.