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End-to-End System-Level Simulations with Retimers for PCIe Gen5 & CXL: A How-To Guide

Casey Morrison  (Systems Engineer, Astera Labs, Inc.)

Elene Chobanyan  (Signal Integrity Engineer, Hewlett Packard Enterprise)

Pegah Alavi  (Director, Keysight)

Location: Ballroom D

Date: Wednesday, January 29

Time: 9:00 am - 9:45 am

Track: 06. System Co-Design: Modeling, Simulation & Measurement Validation, 13. Modeling & Analysis of Interconnects

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

One of the toughest challenges in architecting a state-of-the-art system is knowing—before prototypes are built—that the system will achieve robust high-speed performance on all channels and across environmental conditions. Due to the fast data rate and high-volume nature of its end-equipment PCIe 5.0 presents a unique challenge for system implementers. To maintain control over certain systems costs and/or enable their smooth operation at highest data rates, the usage of Retimers becomes paramount. This paper presents a how-to design guide for common PCIe topologies involving Root Complex, Retimer, and End Point.


This presentation provides a how-to guide for analyzing and optimizing PCI Express 5.0 interconnects with Retimers using an EDA simulation flow and system design best practices. Common PCIe system topology examples are provided, and a start-to-finish analysis methodology is proposed including placement, material selection, and simulation.

Intended Audience

Basic familiarity with signal integrity concepts (insertion loss, crosstalk, reflections, etc.), IBIS-AMI simulations (s-parameters, model parameters, etc.), and Retimers

Presentation File