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Evolution of PCIe: Hardware Components & How They Impact Past, Present & Future Standards

Davi Correia (Signal Integrity Engineer, Carlisle IT)

Emad Soubh (Director of Engineering, Carlisle IT)

Raul Stavoli (Signal Integrity Engineer, Carlisle IT)

Kelsey Fisher (Mechanical Engineer, Carlisle IT)

Location: Ballroom D

Date: Wednesday, January 29

Time: 2:50pm - 3:30pm

Track: 13. Modeling & Analysis of Interconnects, 12. Applying Test & Measurement Methodology

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: All

In this paper, we will show how the combination of different board configurations (edge-coupled versus broadside-coupled), connectors, cable styles and cable terminations affect the performance when it comes to designing systems for PCIe Gen4, Gen5 and Gen6. We will show, through simulations and measurements, which of these components are the bottle necks when it comes to achieving the required specification. We will examine the trade-offs between cost and performance for each combination of board, connector and cable. We will show the results of each component when simulated/measured by itself and when simulated/measured in the full system topology.

Takeaway

We will present different aspects of the PCIe standards, specially related to the physical layer. At the end, the audience should be able to understand how different components (boards, connectors and cables) impact the performance for different PCIe protocols (4.0, 5.0 and 6.0).

Intended Audience

None