DesignCon 2022 Schedule Builder

The pandemic has shifted many digital modernization projects within the internet infrastructure to occur more swiftly. Similar to the way cloud architectures have changed networking in the past decade, we now see rapid transitions to new technologies. In the next 2-3 years the future ethernet speed will evolve toward the 224 Gbps per lane. Consider, at this serial data rate, transition times are about 4 picoseconds and unit intervals are below 10 picoseconds for PAM-4 modulation. The development of reliable end-to-end copper communications channels require careful examination of semiconductor devices, packages, PCBs, connectors, and cable assemblies within this context.

Ensuring proper equalization schemes at both transmitter and receiver ends is a critical step of this strategic goal. This work highlights significant aspects and provides reasonable solutions for achieving feasible channel performances. This includes post-DFE eye opening at a given BER for an actual physical channel and compares to channel operating margin (COM). The objective is to present fine measurement techniques for accurately characterizing the channel, and for adequately developing equalization schemes at both TX and RX sides. This also includes the parametric adjustments to COM methodologies. These techniques are necessary for effectively exploring feasible design solutions

Takeaway

The challenges when attempting to design and test channels at 224 Gbps are clarified in terms of amount of equalization at TX and RX, the experimental equipment, analysis tools required for an effective design and validation workflow, and the required bandwidth of the s-parameters for obtaining good simulation/measurement correlation

Intended Audience

Basic knowledge of Channel Operating Margin, S-parameters