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Finding Reflective Insertion Loss Noise & Reflectionless Insertion Loss

Hansel Dsilva  (Staff Signal Integrity Engineer, Achronix Semiconductor Corporation)

Sasikala J  (Senior Package Design Engineer, Achronix Semiconductor Corporation)

Abhishek Jain  (Senior Design Engineer, Achronix Semiconductor Corporation)

Amit Kumar  (Principal Engineer, Achronix Semiconductor Corporation)

Richard Mellitz  (Distinguished Engineer , Samtec)

Adam Gregory  (Signal Integrity Engineer, Samtec)

Beomtaek Lee  (Senior Principal Engineer , Intel)

Location: Ballroom D

Date: Wednesday, January 29

Time: 2:00pm - 2:40pm

Track: 07. Optimizing High-Speed Serial Design, 13. Modeling & Analysis of Interconnects

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: Intermediate

As work begins in designing interconnects at 112 Gbps, channel specification metrics need to be revisited to ensure that the different parameters that lead to eye opening degradation are quantified realistically. This paper identifies the pitfalls of the insertion loss deviation which utilizes a fitted attenuation profile and is not able to distinguish between the reflections and coupling to resonant structures. This alternate approach utilizes the power scattering matrix theory in finding the insertion loss noise due to reflections by solving simultaneous equations for the zero reflection termination. This physics based approach is ideal for interconnect characterization pertaining to reflections.


Presented is a novel methodology to find reflective insertion loss noise and reflectionless insertion loss. It is an evolution of insertion loss deviation. It provides a means of dissection of loss and reflections from a measured S-parameter insertion loss.

Intended Audience

Basics of the scattering matrix and end-to-end channel simulation.

Presentation Files