designcon is part of the Informa Markets Division of Informa PLC
This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.
April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Se-Jung Moon (IO architect, Intel)
Mohiuddin Mazumder (Senior Principal Engineer, Intel)
Zuoguo Wu (Senior Principal Engineer, Intel)
Karsten Stangel (Analog Engineer, Intel)
Umair Khan (Signal Integrity Engineer, Intel)
Masashi Shimanouchi (Design Engineer, Intel)
Location: Ballroom H
Date: Wednesday, April 6
Time: 9:00 am - 9:45 am
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging, 13. Modeling & Analysis of Interconnects
Format: Technical Session
Theme : Infrastructure
Education Level: Introductory
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: Introductory
PCI SIG (peripheral component interconnect special interest group) adapted the ccICN (component contribution integrated crosstalk noise) for PCIe CEM (card electromechanical) specification in limiting the connector crosstalk for 32Gbps NRZ (non-return to zero). The usage resolved issues and limitations of the traditional methodology based upon the limit line-based specification. When PCIe 6.0 utilizes the PAM-4 modulation scheme, the ccICN is generalized for component crosstalk assessment for PAM-N (pulse-amplitude modulation-N levels). In this paper, we introduce the generalized ccICN methodology and validate.
This paper introduces the generalized ccICN for the PAM-N signaling, which is a metric to capture crosstalk noise at a receiver when a component within a channel creates crosstalk.