DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

Early Bird Registration Now Open till November 30th. Save Up to $300 Today!

DesignCon 2019 Presentation Viewer

Purchase procecdings

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

If you’d like to do a bulk download of all conference presentations or technical papers at once, please click here for conference presentations or click here for full technical papers. For sessions not included in the main conference, click here for Chiphead Theater presentations or click here for sponsored session presentations.

Get Your Game On for Next Generation DRAM: DDR5 and LPDDR5

Perry Keller (Lead Digital Applications and Standards Program, Memory Applications Program Manager, Keysight Technologies)

Location: Great America 1

Date: Wednesday, January 30

Time: 8:30am - 9:10am

Track: Sponsored Sessions

Session Type: Sponsored Session

Vault Recording: TBD

Audience Level: Intermediate

Keysight Technologies

Right on the heels of DDR4, the industry’s next generation of system and mobile memories will drive another paradigm shift for Silicon and system developers. DDR4 required thinking to move beyond the certainty promised by setup and hold timings and voltage margins into the new terrain of random and deterministic jitter and noise as well as bit error rates (BER) that could never be guaranteed to be zero no matter how much margin you had. This is the world of data eyes and statistics. Before DDR4 speeds can be doubled, the statistical eye that people were just getting their minds wrapped around will collapse. Opening it back up requires applying concepts first developed for high speed serial busses like PCI Express to DDR. Memory’s wide, single ended, bidirectional and bursty bus stretches these concepts to their limits and beyond, requiring everyone to up their game. This session will show you how to get your game on so you can master a whole new generation of DRAM.