April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
DesignCon 2022 Schedule Builder
How To Efficiently Build and Analyze Memory Bus to Meet DDR Specification
Speakers:
HeeSoo Lee (DDR/SerDes Product Owner, Keysight Technologies)
Shaishav Pandya (R&D Software Engineer , Keysight Technologies)
Location: Mission City Ballroom B4
Date: Thursday, April 7
Time: 2:50 pm - 3:30 pm
Track: Sponsored Session
Format: Sponsored Session
Education Level: All
Pass Type: 2-Day Pass, All Access Pass, Expo Pass
Vault Recording: TBD
Audience Level: All
Due to ever increasing data demand, the speed grade for memory is now in the multi-gigabit range. Memory bus design becomes a lot more complicated with tighter design margins due to higher crosstalk between vias and traces along with increased inter-symbol interference. It becomes critical to build up an accurate pre-layout model for the bus, testing it against specifications and optimizing it before spinning another PCB layout. To complete the flow, the same analyses can be applied to post-layout memory buses as well. In this webinar, we will discuss the importance of memory channel pre- and post-layout models, how to build them, and how to optimize them to meet design targets.
Takeaway
1.Building Pre-layout memory bus for design space exploration channel models
2. Validating Post-layout channel models to the design standard
3. Using a wizard-driven smart pre-layout workflow for Data and Command/Address buses
