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Jun So Pak (Pricipal Engineer, Samsung Elecronics Co)
Location: Ballroom F
Date: Thursday, January 30
Time: 2:00pm - 2:45pm
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Format: Technical Session
Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!
Vault Recording: TBD
Audience Level: All
This paper is proposing a high bandwidth and accurate RLCG model PEX (parameter extraction) method for 2.5D Si-Interposer Serdes signal channel by considering high loss silicon substrate, which limit capacitance bandwidth below a few GHz, and combining conventional on-/off-chip PEX tools w.r.t their running capacities, which are very strongly related to ultra-wide dimension scales of 2.5D Si-Interposer from sub-micro meters to a few tens micro meters. The proposal gives high accurate model parameters well reflecting silicon environment to BEOL, TSV (through silicon via) capacitance, and C4bump pad, and allows over 10GHz Nyquist frequency signaling by optimizing Si-Interposer Serdes channel designs.
A RLCG model PEX (parameter extraction) method for 2.5D Si-Interposer Serdes signal channel is being proposed by considering high loss silicon substrate and combining conventional on-/off-chip PEX tools w.r.t their running capacities. The proposal gives high accurate model parameters well reflecting silicon environment and allows over 10GHz Nyquist frequency signaling.
This paper is open to all experience levels.