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April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Aleksey Tyshchenko (CEO, Founder, SeriaLink Systems)
Richard Allred (Senior Developer, MathWorks)
Clinton Walker (Vice President Marketing, Alphawave IP)
David Halupka (Founder & Director, SeriaLink Systems)
Tripp Worrell (SI/AMS/SiSoft Development Manager, MathWorks)
Barry Katz (Director RF/EM/SI/AMS / President/CEO, MathWorks / SiSoft)
Adrien Auge (Signal Integrity Engineer, Alphawave IP)
Location: Ballroom G
Date: Thursday, April 7
Time: 3:00 pm - 3:45 pm
Track: 02. Chip I/O & Power Modeling, 07. Optimizing High-Speed Link Design
Format: Technical Session
Theme : High-speed Communications
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
This paper presents IBIS-AMI modeling and correlation methodologies for ADC-based SerDes using two alternative approaches. In the first approach, a COM-representative model is built to accurately capture the SerDes performance and to integrate into the established signal integrity (SI) workflows at the cost of simplifying the SerDes topology. In the second approach, an architecturally representative model is built to accurately reflect the ADC-based architecture and its performance at the cost of simplifying the interface between the model and the SI simulator. These methodologies are extended from conventional symbol-detecting SerDes, which cancel ISI, to maximum likelihood sequence-estimating (MLSE) SerDes that leverage a known amount of ISI to improve the BER. The proposed methodologies are then used to build IBIS-AMI model for a 1-to-112Gb/s multi-standard ADC-based SerDes IP, and to correlate this model with lab measurements.
This paper presents two IBIS-AMI modeling methodologies for ADC-based SerDes, silicon correlation methodology for 1-to-112Gb/s ADC-based SerDes, and IBIS-AMI modeling approach for maximum likelihood sequence estimation (MLSE) in ADC-based SerDes.