April 5-7, 2022|Santa Clara Convention Center| Santa Clara, CA
Speaker:
Jihun Kim (Ph.D candidate, Korea Advanced Institute of Science and Technology)
Authors:
Minsu Kim (Ph.D candidate, Korea Advanced Institute of Science and Technology)
Joungho Kim (Professor, Korea Advanced Institute of Science and Technology)
Hyunwook Park (Graduate Student (PhD), Korea Advanced Institute of Science and Technology)
Jiwon Yoon (Student, Korea Advanced Institute of Science and Technology)
Seonguk Choi (Graduate Student (PhD), Korea Advanced Institute of Science and Technology, KAIST)
Joonsang Park (Ph.D. Candidate, Korea Advanced Institute of Science and Technology)
Haeyoen Rachel Kim (Master Candidate, KAIST)
Keeyoung Son (Graduate Student (PhD), Korea Advanced Institute of Science and Technology)
Seongguk Kim (Ph.D. Candidate, Korea Advanced Institute of Science and Technology)
Daehwan Lho (Graduate Student (PhD), Korea Advanced Institute of Science and Technology)
Keunwoo Kim (Graduate Student (PhD), Korea Advanced Institute of Science and Technology)
Jinwook Song (Staff Engineer, Samsung Electronics)
Kyunguk Kim (Principal Engineer, Samsung Electronics)
Jonggyu Park (Vice President, Samsung Electronics)
Location: Ballroom G
Date: Thursday, April 7
Time: 8:00 am - 8:45 am
Track: 01. Signal & Power Integrity for Single-Multi Die, Interposer & Packaging
Format: Technical Session
Theme : High-speed Communications
Education Level: All
Pass Type: 2-Day Pass, All Access Pass
Vault Recording: TBD
Audience Level: All
As the data rate of PCIe dramatically increases, channel loss has reached the limit. To overcome the channel loss problems of PCIe 6.0., PAM-4 signaling is required to increase the bandwidth. Since the eye-margin of PAM-4 is 1/3 smaller compared to NRZ, controlling the PAM-4 based signaling system is extremely sensitive to parameters of high-speed serial links; the possibility of PAM-4 degrading SI than NRZ arises. Therefore, providing such an effective optimization method is crucial for the improvement of SI characteristics of PAM-4 based signaling system.
In this paper, we propose a novel BO scheme based on DNN objective-regressor for PAM-4 based PCIe 6.0. Our scheme has two main components: (a) BO and (b) DNN-based objective simulator. The BO learns to generate a candidate solution based on data collected from the objective simulator. To construct a fast, accurate and flexible objective simulator, we combine the circuit simulator and DNN model. To be specific, the circuit simulator produces S-parameters from the design solution provided by BO. Then the DNN returns eye-opening from the provided partial information of S-parameter. Since the pre-trained DNN model enables a quick computation of eye-opening, the proposed scheme can overcome the previous limitations of BO scheme.
This paper a novel BO scheme based on deep neural network (DNN) objective-regressor for PAM-4 based PCIe 6.0. The proposed method tunes whole system of PCIe 6.0 including high-speed channel and via in extremely fast speed. The proposed method can be also applied to various system-level interconnection optimization tasks.
This paper a novel BO scheme based on deep neural network (DNN) objective-regressor for PAM-4 based PCIe 6.0. The proposed method tunes whole system of PCIe 6.0 including high-speed channel and via in extremely fast speed. The proposed method can be also applied to various system-level interconnection optimization tasks.