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Impact of Clock Recovery Design on PAM4 Measurements

Pavel Zivny (Domain Expert, Tektronix)

Mark Guenther (Principal Engineer, Tektronix)

Jesse Hawkins (Hardware Designer, Tektronix)

Location: Ballroom B

Date: Thursday, January 30

Time: 11:00am - 11:45am

Track: 08. Measurement, Simulation & Improving Jitter, Noise & BER (Pre & Post FEC), 07. Optimizing High-Speed Serial Design

Format: Technical Session

Pass Type: 2-Day Pass, All-Access Pass, Alumni All-Access Pass - Get your pass now!

Vault Recording: TBD

Audience Level: Advanced

For the case of a PAM4 serial data link we show that the result of the figure of merit measurements of the signals in today's PAM4 links (SNDR, TDECQ) is a function of the detailed architecture of the clock recovery used for the measurements, and on the ISI and other characteristics of the signal. We quantify the impact of this on the error in result of these practical figure-of-merit measurements of PAM4 signal for characterization and compliance test. We present a novel remedy for this undesirable dependency.

Takeaway

Measurements of PAM4 signals are burdened by errors due to differences in clock recovery of the measurement systems. We characterize a class of these errors, describe an error mechanism, and describe and evaluate a remedy for this class of errors.

Intended Audience

Understanding of PAM4 serial data transmission and of its measurements